Today I completed the coding part for the simulation of HDMI2USB. The main aim for this was to check whether the read and write pattern used in DDR2 Ram is optimum. For this I removed all the parts which did not affect the read and write performance of DDR2 Ram like EDID, USB etc. The only problem is that the simulation takes up a lot of time. It takes upto 4 hrs for the calibration of DDR2 ram. I am currently simulating it. I will wake up and check the waveforms.
I think there's supposed to be a simulation model setting you can twiddle to skip or reduce calibration time, though I can't recall anyone confirming if it actually works or not. Worth a try if you haven't looked at it!
ReplyDeleteAre you associated with a university enrolled in the Xilinx University Program? If so, you might be able to get a license to use the non-crippled ISim, which removes the very annoying simulation speed limitation.