1 Week Down!

In the past week I stuck to my goal of improving the fmax of MPEG coder. I tried to run at 105 Mhz(because clock dividers should be integer) but timing constraints failed. Tried a bunch of stuff but didn't succeed. Then I finally ran the MPEG  core at 90 MHz. All timing constraints were met but there was no improvement in the speed which was a bummer. Anyway during weekend I tried an optimisation but was not able to run it successfully on the hardware. The JPEG top module has the following FSM


As you can see, after every frame compressed lumination and chrome tables are written again. Plus because of the OPB interface, there is atleast a cycle long wait for ack. So for every frame 512*2=1024 cycles are wasted when a frames is compressed. So I was trying to change the FSM so that the table writing step is bypassed if there is no command to change the encoding quality. Unfortunately my changes are not working on hardware. I am planning to spend some time on it. Also I plan to check the efficieny of HDMI2USB minus the cypress firmware so that I can test whether or not the cypress is slowing down HDMI2USB. Finally I am planning to start modifying the code for 4:2:0 sub sampling. This will take some time as I need to rewrite the FSM of JPEG core. This will probably take 2 weeks. Hope this week gives me some positive results.